Semiconductor integrated circuits are formed in a body of semiconductor material having active regions therein which are joined in a desired circuit configuration by a plurality of wiring layers laid down on the surface of the body.
Many semiconductor integrated circuits, such as logic circuits, are designed to be tailored, after manufacture, to provide certain logical combinations or meet other selected criteria. To permit such tailoring such circuits are designed with circuit alteration devices, typically and hereinafter referred to as fuses, which are usually in the form of lines that can be physically broken or cut to thereby alter the circuit from its original configuration. This tailoring ability is provided in such circuits, during the circuit design and is included as part of the wiring layers of the circuit.
In the manufacture of the circuit, these wiring layers are deposited and defined and interconnected with conductive vias through a series of well known photolithography and metal etching steps. Each such wiring level is coated with a layer of a glassy protective material, known as a passivation layer, which protects and insulates the wiring of each layer. The creation of integrated circuits with such multiple wiring layers is well known to the semiconductor art.
In such circuits it has been found that if the lines or fuses are formed with positive side slopes, they offer distinct advantages over line with negatively sloped side wall. The advantages are especially realized during the fabrication of the wiring levels, the subsequent deposition of the passivation layer, and the formation of the interconnection vias.
In some circuits, such as CMOS logic circuits, the fuses, designed in the circuit are usually formed in regular arrays in the upper most layers of wiring and in a position such that other wiring is not placed immediately thereover. In such arrays the fuses are often aligned in parallel rows and placed as closely together as is possible. By opening selected ones of these fuses the logic elements of the circuits can be arranged in different combinations to perform different logic functions.
These fuses are typically opened by applying a laser pulse of sufficient size, duration and power as to superheat and vaporize the metal forming the fuse. This superheating of the fuse and its vaporization fractures and blows away a portion of the overlying glassy protective layer creating a saucer shaped crater in the protective layer. When the protective layer ruptures, cracks can radiate outwardly causing additional damage such as breakage of or the uncovering of adjacent elements. Such uncovering of the adjacent elements can cause subsequent corrosion and premature failure of the circuit. Furthermore, there is no known means of repairing any of the adjacent circuit elements accidentally altered by the blowing of an adjacent fuse.
It has been found that when the fuse, being blown, has sides with a positive slope these effects are worsened because the beam, used to vaporize the fuse, is reflected therefrom and can cause partial melting and reflowing of adjacent circuit elements altering their resistive and capacitive characteristics and hence the circuit to which they are connected.
To prevent such damage to the adjacent elements, the prior art could provide no solution except that of increasing the inter-element distance between the fuse, and the adjacent elements. This solution is undesirable. The entire direction in the integrated circuit art has been directed towards reducing the size of the circuit and hence reducing inter-element dimensions to the smallest level possible. Thus, the only available solution was unacceptable but, until the present invention, there has been no other.
Accordingly, there now exists a need for an improved circuit arrangement which avoids all the above described problems associated with the blowing of such fuses as found in the prior art. The present invention, achieves these desirable results, by preventing both the beam energy and the effects of the fuse blowing to reach or affect any adjacent element in the circuit while maintaining the presently achievable, minimum, inter-element dimensions and all the other known advantages of such fuse arrays.